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a 400 msps 14-bit, 1.8v cmos direct digital synthesizer preliminary technical data AD9953 rev. prb 1/30/2003 information furnished by analog dev i ces is believ ed to be accurate and reliable. how e v e r, no responsibility is assumed by analog dev i ces for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherw i se under any patent or patent rights of analog dev i ces. trademarks and registered trademarks are the property of their respectiv e companies. one technol ogy way , p. o. box 9106, nor w ood, m a 02062-9106, u. s. a . tel : 781/ 329-4700 www.anal og.com fax: 781/326-8703 ? 2002 a n alog dev i ces, inc. a ll rights reserv e d. features 400 msps internal clock speed in teg r ated 14-b i t d/a co n v erter pro g r ammab l e p h ase/amp litu d e d i th erin g 3 2 - bit tuning word ph ase no ise < = -125 d b c/hz @ 1khz o ffset (da c o u t p u t) excellen t dy n a mic perfo rman ce 80d b sf dr @ 130mhz (+ /- 100khz offset) a o u t serial i/o control 1 . 8 v pow e r supply softw a r e a nd ha rdw a re c ontrolle d pow e r dow n 48-lead epa d-t q f p p ackag e line a r a nd non-line a r fre que nc y s w e e p ing c a p a b ility in teg r ated 1024x32 w o rd ra m support for 5 v input le v e ls on mos t digita l inputs pll refclk multiplier (4x to 20x) internal oscillator, can be driv en by a single cry s tal phase modulation capability multi-chip synchronization applications a g ile l.o. frequency sy nthesis fm chirp sourc e for ra da r a nd sc a nning sy s t e m s a u tomotiv e radar t est an d measu remen t eq u i p m en t psk/fsk/ra m pe d fsk modula t ion functional block diagram da c dac i - set aout aout syst e m cl ock tim i ng & cont r o l logic i/ o updat e ref c lk sync out io po rt cont rol reg i st ers sy n c reset m u x 4x- 20x c l o c k m u lt ipler s yst em cl ock refc lk o s c illa to r/ b u f f e r syn c 0 4 m u x phase ac cumul a tor co s ( x ) ph a s e off set dd s c o re 19 z -1 z -1 dd s clock ps<1:0> osk pwrd wn sta t ic r a m 10 24 x 32 32 10 3 32 ram da t a m u x 14 m u x ra m da t a < 3 1 : 1 8 > 32 32 32 14 32 cryst al out ena b le 14 ph ase a c c u mu l a t o r r ese t fr equ e n cy t unin g wor d dd s c l o c k ram c ont rol ra m a dd r ram d a t a
preliminary technical data AD9953 rev. prb 1/30/03 page 2 analog devices, inc. general description the AD9953 is a direct digital synthesizer (dds) featuring a 14-bit dac operating up to 400msps. the AD9953 uses advanced dds technology, coupled with an internal high-speed, high performance d/a converter to form a digitally- programmable, complete high-fre quency synthesizer capable of generating a frequency-agile anal og output sinusoidal waveform at up to 200 mhz. the AD9953 is designed to provide fast frequency hopping and fine tuning resolution (32-bit frequency tuning word). the frequency tuning and control words are loaded into the AD9953 via a serial i/o port. the AD9953 includes an integrated 1024x32 static ram to support flexible frequency sweep capability in several modes. the AD9953 is specified to operate over the extended industrial temperature range of -40 to +85c. absolute maximum ratings 1 maximum junction temp. ............................. +150 c storage temperatu re ................................... -65 c to +1 50 c vs ............................................................................ +4 v operating temp. ........................... ................. -40 c to +85 c digital input voltage ............................... -0.7 v to +vs lead temp. ( 10 sec. soldering) ............................. ...... +300 c digital output current ....................................... 5 ma t ja .................................................................................. 38c/w t jc 15 c/w * absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. contents functional block diagram 1 general description 2 ad9954 preliminary electrical specifications 4 AD9953 pinmap 7 pin name 8 i/o 8 component blocks 10 dds core 10 phase truncation 11 clock input 11 phase locked loop (pll) 12 dac output 12 serial io port 12 register maps and descriptions 13 control register bit descriptions 16 control function register #1 (cfr1) 16 control function register #2 (cfr2) error! bookmark not defined. control function register #2 (cfr2) 21 other register descriptions 22 amplitude scale factor (asf) 22 amplitude ramp rate (arr) 22 frequency tuning word 0 (ftw0) 23 phase offset word (pow) 23
preliminary technical data AD9953 frequency tuning word 1 (ftw1) 23 ram segm ent control words 0,1,2,3 (rscw0) (rscw1) (rscw2), (rscw3) 23 ram 23 modes of operation 24 single tone mode 24 ram controlled modes of operation 24 direct switch mode 24 ram p -up mode 25 bi-directional ram p mode 25 continuous bi-directional ram p mode 26 continuous re-circulate mode 27 ram controlled modes of operation sum m a ry 28 internal profile control 28 program m i ng AD9953 features 30 phase offset control 30 phase/am plitude dithering 30 shaped on-off keying 31 auto shaped on-off keying m ode operation: 32 osk ramp rate timer 33 external shaped on-off keying m ode operation: 33 synchronization; register updates (i/o update) 34 functionality of the syncclk and i/o update 34 figure d- i/o synchroni zation block diagram 35 figure e - i/o synchroni zation tim i ng diagram 35 synchronizing multiple AD9953s 36 using a single crystal to driv e multiple AD9953 clock inputs 36 serial port operation 37 instruction byte 38 serial interface port pin description 39 msb/lsb transqfers 39 example operation 40 ram i/o via serial port 40 notes on serial port operation 41 power down functions of the AD9953 41 rev . p r b 1/30/03 page 3 analog devices , inc.
preliminary technical data AD9953 rev. prb 1/30/03 page 4 analog devices, inc. AD9953 preliminary electrical specifications (unless otherwise noted: (v s =+1.8 v r 5%, r set =1.96 k : , external reference clock frequency = 20 mhz with refclk multiplier enabled at 20 u ) parameter temp test level AD9953 min typ max units ref clock input characteristics frequency range refclk multiplier disabled full vi 1 400 mhz refclk multiplier enabled at 4x full vi 20 100 mhz refclk multiplier enabled at 20x full vi 4 20 mhz input capacitance +25c v 3 pf input impedance +25c v 100 m : duty cycle +25c v 50 % duty cycle with refclk multiplier enabled +25c v 35 65 % dac output characteristics resolution 14 bits full scale output current +25c 5 10 15 ma gain error +25c i -10 +10 %fs output offset +25c i 0.6 p a differential nonlinearity +25c v 1 lsb integral nonlinearity +25c v 2 lsb output capacitance +25c v 5 pf residual phase noise @ 1 khz offset, 40 mhz a out refclk multiplier enabled @ 20 u +25c v -89 dbc/hz refclk multiplier enabled @ 4 u +25c v -105 dbc/hz refclk multiplier disabled +25c v -116 dbc/hz voltage compliance range +25c i avdd- 0.375 avdd + 0.25v v wideband sfdr: 1 ? 20 mhz analog out +25c v dbc 20 ? 40 mhz analog out +25c v dbc 40 ? 60 mhz analog out +25c v dbc 60 ? 80 mhz analog out +25c v dbc 80 ? 100 mhz analog out +25c v dbc 100 ? 120 mhz analog out +25c v dbc 120 ? 140 mhz analog out +25c v dbc 140 ? 160 mhz analog out +25c v dbc narrow band sfdr 10 mhz analog out (1 mhz) +25c v dbc 10 mhz analog out (250 khz) +25c v dbc 10 mhz analog out ( 50 khz) +25c v dbc 10 mhz analog out ( 10 khz) +25c v dbc 65 mhz analog out ( 1 mhz) +25c v dbc 65 mhz analog out ( 250 khz) +25c v dbc 65 mhz analog out ( 50 khz) +25c v dbc 65 mhz analog out ( 10 khz) +25c v dbc 80 mhz analog out ( 1 mhz) +25c v dbc 80 mhz analog out ( 250 khz) +25c v dbc 80 mhz analog out ( 50 khz) +25c v dbc 80 mhz analog out ( 10 khz) +25c v dbc 100 mhz analog out ( 1 mhz) +25c v dbc 100 mhz analog out ( 250 khz) +25c v dbc 100 mhz analog out ( 50 khz) +25c v dbc 100 mhz analog out ( 10 khz) +25c v dbc 120 mhz analog out ( 1 mhz) +25c v dbc 120 mhz analog out ( 250 khz) +25c v dbc 120 mhz analog out ( 50 khz) +25c v dbc 120 mhz analog out ( 10 khz) +25c v dbc 140 mhz analog out ( 1 mhz) +25c v dbc 140 mhz analog out ( 250 khz) +25c v dbc 140 mhz analog out ( 50 khz) +25c v dbc 140 mhz analog out ( 10 khz) +25c v dbc 160 mhz analog out ( 1 mhz) +25c v dbc 160 mhz analog out ( 250 khz) +25c v dbc
preliminary technical data AD9953 p a r a m e t e r t e m p tes t min typ m a x un its l e v e l 160 mhz analog out ( 50 khz) +25c v dbc 160mhz analog out ( 10 khz) +25c v dbc timing characteristics serial co n t ro l bu s m a xim u m fr equency m i nim u m clock pulse w i dth l o w ( t pwl ) m i nim u m clock pulse w i dth high ( t pwh ) m a xim u m clock rise/fall t i m e m i n i mu m d a t a s e t u p t i me ( t ds ) m i n i mu m d a t a h o l d t i me ( t dh ) m a x i mu m d a t a v a l i d t i me ( t dv ) w a ke- u p t i m e 2 minim u m reset pulsewidth high (t rh ) full full full full full full full full full full iv iv iv iv iv iv iv iv iv iv 7 7 10 0 25 5 5 1 25 mhz ns ns ns ns ns ns ms sysclk cycles 3 cm os l ogi c i n put s logic ? 1 ? voltage @ dvdd = 1.8v logic ? 0 ? voltage @ dvdd = 1.8v logic ? 1 ? voltage @ dvdd = 3.3v logic ? 0 ? voltage @ dvdd = 3.3v l ogic ?1? cur r e nt l ogic ?0? cur r e nt i nput capacitance +25 c +25 c +25 c +25 c +25 c +25 c +25 c i i i i v 1. 25 2. 2 3 0. 6 0. 8 12 12 v v v v a a pf cm os l ogi c out p ut s (1m a load) dvdd=1.8v l ogic ?1? voltage l ogic ?0? voltage +25 c +25 c i i 1. 35 0. 4 v v power supply +vs cu rren t full oper ating conditions 400 m h z clock 120 m h z clock power - d own m ode full-sleep mode +25 c +25 c +25 c +25 c +25 c +25 c i i i i i i 30 tbd tbd tbd tbd tbd ma ma ma ma ma ma rev . p r b 1/30/03 page 5 analog devices , inc.
preliminary technical data AD9953 notes 1 absolute m a xim u m ratings are lim iting values to be applied i ndividually, and be yond which the serviceability of the circuit m a y be im paired. functional operability under any of these conditions is not necessarily im plied. exposure of absolute m a xim u m ratin g co n d itio n s fo r ex ten d e d p e rio d s o f tim e affect d e v i ce reliab ility. 2 w a ke-up ti m e refers t o recovery from anal og power down m ode s (see power down m odes of operat i on). the l ongest t i m e req u i red is fo r th e referen ce clo c k mu ltip lier pll to lo ck u p (if it is b e in g u s ed ). th e w a k e -up tim e assu m e s th at th ere is n o capacitor on dac_bp, and that the recom m e nded pll loop filter values are used. 3 sysclk refers to the actual clock freque ncy used on-chip by the ad9954. if the reference clock multiplier is used to m u ltip ly th e ex tern al referen ce freq u e n c y, th en th e sysclk freq u e n c y is th e ex tern al freq u e n c y m u ltip lied b y th e referen ce clo c k mu ltip lier m u ltip licatio n facto r . if th e referen ce clo c k mu ltip lier is n o t u s ed , th en th e sysclk freq u e n c y is th e sam e as the external refclk frequency. ex planation of test levels i ? 100% product i on test ed. ii ? 100% product i on test ed at +25 c and sam p le tested at specified tem p eratures. iii ? sam p le tested only . iv ? param e t e r i s guarant eed by desi gn and charact eri zat i on t e st i ng. v ? param e t e r i s a t y pi cal val u e onl y . vi ? devi ces are 100% product i on t e st ed at +25c and guara nt eed by desi gn and charact eri zat i on t e st i ng for i ndust r i a l operat i ng t e m p erat ure range. ordering guide model temperature range package description package option AD9953asv -40c t o +85c 48-l ead qfp epad sv-48 AD9953pc b + 2 5 c eval uat i o n b o a r d caution esd (electrostatic discharge) s ensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge w i thout detection. although the AD9953 f eatures proprietary esd protection circuitry , permanent damage may occur on devices subjected to high-energy electrostatic discharges. t herefore, proper esd prec autions are recommended to avoid performance degradation or loss of functionality . rev . p r b 1/30/03 page 6 analog devices , inc.
preliminary technical data AD9953 AD9953 pinmap avd d os c/ r e f c l k os cb / r e f c l kb ag n d a d 9953 pi nout 48 leads 35 34 33 32 31 30 29 27 26 25 23 22 21 20 18 17 16 15 14 12 11 10 13 47 46 45 44 43 42 41 40 39 48 11 36 38 37 28 24 19 9 8 7 6 5 4 3 2 1 d a c b p d a c _ r s e t s y n c c l k dv dd i/o u p d a te d g n d p s 1 o s k s c l k _ c s res e t s d i o d v d d _ i o dgnd s d o i o s y n c lo o p _f i l t e r dgnd dv dd p s 0 pw r d w n c t l a g n d a v d d a v d d a g n d i o u t b i o u t a g n d a v d d c l km odes e l e ct cr y s t a l ou t ag n d ag n d nc avd d ag n d ag n d s y n c i n a g n d a v d d ag n d avd d avd d avd d figure 1 AD9953 pinmap rev . p r b 1/30/03 page 7 analog devices , inc.
preliminary technical data AD9953 hardw a re pin descriptions pin # pin name i/o description 1 i/o update i the rising edge transfers the contents of the internal buffer m e m o ry to the io registers. 2,34 dvdd i digital power supply pins. 3,33, 42 dgnd i digital power ground pins. 4,6, 13,16, 18,19, 25,27, 29 avdd i analog power supply pins. 5,7, 14,15, 17,22, 26, 30,31 32 agnd i analog power ground pins. 8 oscb/refclkb i com p lem e ntary reference clock/oscillator input (400mhz m a x.). note: w h en the refclk port is operated in single-ended m ode, then refclkb should be decoupled to avdd with a 0.1 f capacitor. 9 osc/refclk i reference clock/oscillator input (400 mhz m a x.). see clock input section of datasheet for details on the refclk/oscillator operation. 10 crystal out o output of the oscillator section. 11 clkmodeselect i control pin for the oscillator section. w h en high, the oscillator section is enabled. w h en low, the oscillator section is bypassed. 12 loop_filter i this pin provides the connection for the external zero com p ensation network of the refclk multiplier?s pll loop filter. the network consists of a 1k ohm resistor in series with a 0.1 f capacitor tied to avdd. 20 ioutb o com p lem e ntary dac output. 2 1 i o u t o d a c o u t p u t . 23 dacbp i dac ?biasline? decoupling pin. 2 4 d a c _ r s e t i a resistor (3.85k ? nom inal) connected from agnd to dac_rset establishes the ref e rence current f o r the dac. 2 8 n c o n o c o n n e c t . 35 pwrdwnctl i input pin used as an external power down control. see the external power down control section of this docum ent for details. rev . p r b 1/30/03 page 8 analog devices , inc.
preliminary technical data AD9953 36 reset i active high hardware reset pin. assertion of the reset pin forces the AD9953 to the initial state, as described in the io port register m a p. 3 7 i o s y n c i asynchronous active high reset of the serial port controller. when high, the current io operation is im m e diately term inated enabling a new io operation to commence once iosync is returned low 3 8 s d o o when operating the i/o port as a 3-wire serial port this pin serves as the serial data output. when operated as a 2-wire serial port this pin is the unused and can be left unconnected. 3 9 c s - b a r i this pin functions as an active low chip select that allows multiple devices to share the io bus. 4 0 s c l k i this pin functions as the serial data clock for io operations 4 1 s d i o i / o when operating the i/o port as a 3-wire serial port this pin serves as the serial data input , only. when operated as a 2-wire serial port this pin is the bi- directional serial data pin. 43 dvdd_i/o i digital power supply (for io cells only, 3.3v optional) 4 4 s y n c _ i n i input signal used to synchronize multiple AD9953s. this input is connected to the sync_clk output of a different AD9953. 4 5 s y n c _ c l k o clock output pin, which serv es as a synchronizer for external hardware. 4 6 o s k i input pin used to control the direction of the shaped on-off keying function when program m e d for operation. osk is synchronous to the sync_clk pin. when osk is not pr ogram m e d, this pin should be tied to dgnd. 4 7 , 4 8 p s 0 , p s 1 i input pins used to select one of the four internal profiles. profile<1:0>are synchronous to the sync_clk pin. any change in these inputs transfers the contents of the internal buffer memory to the io registers (sends an internal i/o update). table 1 hardware pin descriptions rev . p r b 1/30/03 page 9 analog devices , inc.
preliminary technical data AD9953 theory of operation component blocks dds core the output frequency (f o ) of the dds is a function of the frequency of system clock ( sysclk ), the value of the frequency tuning word (ftw ), and the capacity of the accumulator (2 32 , in this case). the exact relationship is given below with f s defined as the frequency of sysclk. f o = (ftw)(f s ) / 2 32 { 0 ftw 2 31 f o = f s* ( 1 ? ( ftw / 2 32 ) ) { 2 31 < ftw < 2 32 -1 the AD9953 frequency tuning word(s) are unsi gned num bers, where 80000000( hex) represents the highest output frequency possible, com m only re ferred to as the nyquist frequency. values ranging from than 80000001(hex) to ffffffff (hex) w ill be expressed as aliased frequencies less than nyquist. an example using a 3-bit phase ac cumulator will illustrate this principle. for a tuning word of 001, the phase accumulator output (p ao) increments from all zeros to all ones and repeats when the accumulator overfl ows after clock cycle number 8. for the tuning word of 111, the phase accumulator output (pao) decrements fro m all ones to all zeros and repeats when the accumulator overflows after clock cycle number 8. while the phase accumulator outputs are ?reversed? with respect to clock cycles, the outputs provide identical inputs to the phase to am plitude converter, which m e ans the dds output frequencies are identical. mathem atically, for a 3-bit accum ulator, the following equations apply: f o = f s* (ftw / 2 3 ) { 0 ftw 2 2 f o = f s* ( 1 ? ( ftw / 2 3 ) ) { 2 2 < ftw < 2 3 -1 for the 001 frequency tuning word: fout = fs * 1/2 3 = 1/8*fs and for t h e 111 frequency t uni ng word: fout = fs * (1 ? 7/8) = 1/8*fs the value at the output of the phase accumulator is translated to an amplitude value via the cos(x) functional block and routed to the dac. rev . p r b 1/30/03 page 10 analog devices , inc.
preliminary technical data AD9953 in certain applications it is desirable to force the output signal to zero phase. sim p ly setting the ftw to 0 does not accomplish this. it only results in the dds core holding its current phase value. thus, a control bit is required to for ce the phase accumulator output to zero. at power up the clear phase accumulator bit is set to logic one but the buffe r memory for this bit is cleared (logic zero). therefore, upon power up, the phase accumulator will remain clear until the first i/o update is issued. phase truncat i on the 32-bit phase values generated by the phase accu mulator are truncated to 19 bits prior to the cos(x) block. that is, the 19 m o st significant bits of phase are retained for subsequent processing. this is typical of standard dds architecture and is a trade off between hardware complexity and spurious performance. it can be shown that 19-bit phase resolution is sufficient to yield 14-bit am plitude resolution with an error of less than ? lsb. the decision to truncate at 19 bits of phase guarantees the phase error of the cos(x) block to be less than the phase error associated with the amplitude resolution of the 14-bit dac. clock input the AD9953 supports various clock m e thodologies. support for differe ntial or single-ended input clocks, enabling of an on-chip oscillator a nd/or phase-locked loop (pll) multiplier are all controlled via user program m a ble bits. the ad 9953 m a y be configured in one of six operating m odes to generate the system clock. the m ode s are configured using the clkmodeselect pin, cfr1<4>, and cfr2<7:3>. connecting the exte rnal pin clkmodeselect to logic high enables the on-chip crystal oscillator circuit. with th e on-chip oscillator enabled, users of the AD9953 connect an external crystal to the refclk and refclkb inputs to produce a low frequency reference clock in the range of 20-30mhz. the signa l generated by the oscillator is buffered before it is delivered to the rest of th e chip. this buffered signal is available via the crystal out pin. bit cfr1<4> can be used to enable or disable the buffer, turning on or off the system clock. the oscillator itself is not powered down in order to avoid long start-up times associated with turning on a crystal oscillator. writing bit cfr2<1> to l ogic high enables the crystal oscillator output buffer. logic low at cfr2<1> disables the oscillator output buffer. connecting clkmodeselect to logic low disables the on-chip oscillator and the oscillator output buffer. with the oscillator disabl ed an external oscillator must provide the refclk and/or refclkb signals. for differential operation these pins are driven with com p lem e ntary signals. for single-ended operation a 0.1uf capacitor should be connected between the unused pin and the positive power supply. with the capacitor in place th e clock input pin bias voltage is 1.35v. in addition, the pll may be used to multiply the re ference frequency by an integer value in the range of the 4 to 20. rev . p r b 1/30/03 page 11 analog devices , inc.
preliminary technical data AD9953 the modes of operation are summarized in the table below. please note the pll multiplier is controlled via the cfr2<7:3> bits, i ndependently of the cfr2<0> bit. c l k m o d e s e l e c t c f r 1 < 4 > c f r 2 < 7 : 3 > s y s t e m clock frequency range (mhz) high low 3 < m < 21 f clk = f osc x m 80 < f clk < 400 high low m < 4 or m > 20 f clk = f osc 20 < f clk < 30 h i g h h i g h x f clk = 0 f clk = 0 low x 3 < m < 21 f clk = f ref x m 80 < f clk < 400 low x m < 4 or m > 20 f clk = f ref 5 < f clk < 400 table 2 clock input modes of operation phase locked loop (pll) the pll allows multiplication of the refclk freque ncy. control of the pll is accomplished by programming the 5-bit refclk multiplier portion of control function register #2, bits <7:3>. when programmed for values ranging from 04h ? 14h (4-20 decimal), the pll multiplies the refclk input frequency by the co rresponding decim a l value. th e m a xim u m output frequency of the pll is restricted to 400mhz, however. whenev er the pll value is changed, the user should be aware that time must be allocated to a llow the pll to lock (approximately 1ms). the pll is bypassed by program m i ng a value outsi de the range of 4-20 (decim al). when bypassed, the pll is shut down to conserve power. dac output the AD9953 incorporates an integrated 14-bit current output dac. two com p lem e ntary outputs provide a com b ined full-scale output current (i out ). differential outputs reduce the am ount of com m on-m ode noise that m i ght be present at the dac output, offering the advantage of an increased signal-to-noise ratio. the full-scale current is controlled by m e ans of an external resistor (r set ) connected between the dac_rset pin and th e dac ground (agnd). the full-scale current is proportional to the resistor value as follows: r set = 39.19/i out the m a xim u m full-scale output current of the com b ined dac outputs is 15m a, but lim iting the output to 10ma provides the best spurious-fre e-dynamic-range (sfdr) performance. the dac output com p liance range is avdd+0.250v to avdd-375v. voltages developed beyond this range will cause excessive dac distortion and coul d potentially damage the dac output circuitry. proper attention should be paid to the load term ination to keep the output voltage within this compliance range. serial io port rev . p r b 1/30/03 page 12 analog devices , inc.
preliminary technical data AD9953 the AD9953 serial port is a flexible, synchronous serial com m unications port allowing easy interface to many industry standard micro-controlle rs and microprocessors. the serial i/o port is com p atible with m o st synchronous transfer fo rm ats, including both the motorola 6905/11 spi and intel 8051 ssr protocols. the interface allows read/write access to all regist ers that configure the AD9953. msb first or lsb first transfer formats are supported. in add ition, the AD9953?s serial interface port can be configured as a single pin i/o (sdio), which allows a two-wire interface or two unidirectional pins for in/out (sdio/sdo), which enables a three wire interface. two optional pins (iosync and csb) enable greater flexibility for system design-in of the AD9953. register map and descriptions the register map is listed in the following table. the serial address num bers associated with each of the registers are shown in hexadecimal fo rmat. angle brackets <> are used to reference specific bits or ranges of bits. for example, <3 > designates bit 3 while <7:3> designates the range of bits from 7 down to 3, inclusive. rev . p r b 1/30/03 page 13 analog devices , inc.
preliminary technical data AD9953 AD9953 register map regis t er name (s erial addr e ss) bit range (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value or profile < 7 : 0 > d i g i t a l powe r down not used dac powe r down clock input power dwn external powe r down mode not used sy nc clk out disable not used 00h < 1 5 : 8 > n o t u s e d a u t o c l r fre q . accum autoclr p h as e accum enable sine output clear fre q accum . clear p h as e accum . sdio input only ls b first 00h < 2 3 : 1 6 > a u t o m a t i c sy nc enable software manual sy nc not used amplitude dither enable p h as e dither en<3> p h as e dither en<2> p h as e dither en<1> p h as e dither en<0> 00h control function register #1 ( cfr1 ) (00h) < 3 1 : 2 4 > r a m enable ram de st. is p h as e word internal profile control <2:0> load arr @i/o ud osk enable auto osk key i ng 00h <7:0> refclk multiplier 00h or 01h or 02h or 03h: by pass multiplier 04h ?14h: 4x ? 20x m u ltiplication vco gain charge pump control <1:0> 00h <15:8> not use d high s p eed sy nc enable hardware manual sy nc enable cry s tal out pin active dac prime data disable 00h control function register #2 (cfr2) (01h) <23:16> not use d 00h <7:0> amplitude scale fact or register <7:0> 00h amplitude s cale f actor ( asf ) (02h) <15:8> auto ramp rate speed control <1:0> amplitude scale factor register <13:8> 00h amplitude ramp rate (arr) (03h) < 7 : 0 > am plitude ram p rate register <7:0> 00h <7:0> frequency tuning word #0 <7:0> 00h < 1 5 : 8 > f r e q u e n c y tuni ng word #0 <15:8> 00h < 2 3 : 1 6 > f r e q u e n c y tuni ng word #0 <23:16> 00h frequency tuning word ( ftw0 ) (04h) < 3 1 : 2 4 > f r e q u e n c y tuni ng word #0 <31:24> 00h <7:0> p h as e offs et w o rd #0 <7:0> 00h p h as e offset word ( pow0 ) (05h) <15:8> not used<1:0> phase offset word #0 <13:8> 00h rev . p r b 1/30/03 page 14 analog devices , inc.
preliminary technical data AD9953 < 7 : 0 > ram segment 0 mode control <2:0> no dwell active ram segment 0 beginning address <9:6> ps0= 0 ps1= 0 < 1 5 : 8 > ram segment 0 beginning address <5:0> ram segment 0 final address <9:8> ps0= 0 ps1= 0 <23:16> ram segment 0 final address <7:0> ps0=0 ps1= 0 <31:24> ram segment 0 addre ss ramp rate <15:8> ps0=0 ps1= 0 ram se gme n t control word #0 ( rscw0 ) (07h) <39:32> ram segment 0 address ramp rate <7:0> ps0=0 ps1= 0 <7:0> ram segment 1 mode control <2:0> no dwell active ram segment 1 beginning address <9:6> ps0= 1 ps1= 0 <15:8> ram segment 1 beginning address <5:0> ram segment 1 final address <9:8> ps0= 1 ps1= 0 <23:16> ram segment 1 final address <7:0> ps0= 1 ps1= 0 <31:24> ram segment 1address ramp rate <15:8> ps0= 1 ps1= 0 ram se gme n t control word #1 ( rscw1 ) (08h) <39:32> ram segment 1 address ramp rate <7:0> ps0= 1 ps1= 0 <7:0> ram segment 2 mode control <2:0> no dwell active ram segment 2 beginning address <9:6> ps0= 0 ps1= 1 <15:8> ram segment 2 beginning address <5:0> ram segment 2 final address <9:8> ps0= 0 ps1= 1 <23:16> ram segment 2 final address <7:0> ps0=0 ps1= 1 <31:24> ram segment 2 address ra mp rate <15:8> ps0=0 ps1= 1 ram se gme n t control word #2 ( rscw2 ) (09h) <39:32> ram segment 2 address ramp rate <7:0> ps0=0 ps1= 1 <7:0> ram segm ent 3 mode control <2:0> no dwell active ram segment 3 beginning address <9:6> ps0=1 ps1= 1 <15:8> ram segment 3 beginning address <5:0> ram segment 3 final address <9:8> ps0= 1 ps1= 1 <23:16> ram segment 3 final address <7:0> ps0=1 ps1= 1 <31:24> ram segment 3 addre ss ramp rate <15:8> ps0=1 ps1= 1 ram se gme n t control word #3 ( rscw3 ) (0ah) <39:32> ram segment 3 address ramp rate <7:0> ps0=1 ps1= 1 ram (0bh) <31:0> ram [1023:0] <31:0> (read instructions write out ram signature register data) - rev . p r b 1/30/03 page 15 analog devices , inc.
preliminary technical data AD9953 control register bit descriptions control functi on regi ster #1 (cfr1) the cfr1 is used to control the various func tions, features, and m odes of the ad9954. the functionality of each bit is detailed below. cfr1<31>: ram enable bit. when cfr1<31> = 0 (default). when cfr1<31> is inactive, the ram is disabled for operation. either single tone m ode of operation or linear sweep m ode of operations is enabled. when cfr1<31> = 1, if cfr1<31> is ac tive, the ram is enabled for operation. access control for norm a l operation is contro lled via the m ode control bits of the rscw for the current profile. cfr1<30>: ram destination bit. cfr1<30> = 0 (default) if cfr1<31> is active, a logic 0 on the ram destination bit (cfr1<30>=0) configures the ad9954 su ch that ram output drives the phase accumulator (i.e. is the frequency tuning wo rd). if cfr1<31> is inactive, cfr1<30> is a don?t care. cfr1<30> = 1 if cfr1<31> is active, a logic 1 on the ram destination bit (cfr1<30>=1) configures the ad9954 such that ram output drives the phase- offset adder (i.e. sets the phase offset of the dds core). cfr1<29:27>: internal profile control bits. these bits cause the profile bits to be ignored and put the ad9954 into an autom a tic ?profile loop sequence? that allows the user to im plem ent a frequency/phase com posite sweep that runs without external inputs. see the internal profile control section of this document for details. cfr1<26>: amplitude ramp rate load control bit. when cfr1<26> = 0 (default) , the am plitude ram p rate tim er is loaded only upon tim eout (tim er ==1) and is not loaded due to an i/o update input signal. when cfr1<26> = 1, the am plitude ram p rate tim er is loaded upon tim eout (tim er ==1) or at the tim e of an i/o update input signal. rev . p r b 1/30/03 page 16 analog devices , inc.
preliminary technical data AD9953 cfr1<25>: shaped on-off keying enable bit. when cfr1<25> = 0 (d efa u lt,) shaped on-off keying is bypassed. when cfr1<25> = 1, shaped on-off ke ying is enabled. when enabled, cfr1<24> controls the m ode of operation for this function. cfr1<24>: auto shaped on-off keying enable bit (only valid when cfr1<25> is active high). when cfr1<24> = 0 (default). when cfr1<25> is active, a logic 0 on cfr1<24> enables the manual shaped on -off keying operation. see the shaped on-off keying section of this document for details. when cfr1<24> = 1, if cfr1<25> is ac tive, a logic 1 on cfr1<24> enables the auto shaped on-off keying operation. see the shaped on-off keying section of this document for details. cfr1<23>: automatic synchronization enable bit. when cfr1<23> = 0 (default), the automatic synchronization feature is inactive. when cfr1<23> = 1, the autom a tic sync hronization feature is active. see the synchroniz ing multiple AD9953s section of this document for details. cfr1<22>: software manual synchronization bit. when cfr1<22> = 0 (default), the manual synchronization of multiple AD9953s feature is inactive. when cfr1<22> = 1, the software cont rolled manual synchronization of multiple ad9954s feature is executed. the sync_c lk rising edge is advanced by one sysclk cycle and this bit is cleared. to advance the rising edge multiple times, this bit needs to be set fo r each advance. see the synchroniz ing multiple AD9953s section of this document for details. . rev . p r b 1/30/03 page 17 analog devices , inc.
preliminary technical data AD9953 cfr1<20>: amplitude dither enable bit. when cfr1<20> = 0 (default) , am plitude dithering is disabled. when cfr1<20> = 1, am plitude dithering is enabled. cfr1<19>: phase bit <16> dither enable bit. when cfr1<19> = 0 (default) , phase dithering for truncated phase words, bit 16 of <31:13>, is disabled. when cfr1<19> = 1, phase dithering for truncated phase words, bit 16 of <31:13>, is enabled. cfr1<18>: phase bit <15> dither enable bit. when cfr1<18> = 0 (default) , phase dithering for truncated phase words, bit 15 of <31:13>, is disabled. when cfr1<18> = 1, phase dithering for truncated phase words, bit 15 of <31:13>, is enabled. cfr1<17>: phase bit <14> dither enable bit. when cfr1<17> = 0 (default) , phase dithering for truncated phase words, bit 14 of <31:13>, is disabled. when cfr1<17> = 1, phase dithering for truncated phase words, bit 14 of <31:13>, is enabled. cfr1<16>: phase bit <13> dither enable bit. when cfr1<16> = 0 (default) , phase dithering for truncated phase words, bit 13 of <31:13>, is disabled. when cfr1<16> = 1, phase dithering for truncated phase words, bit 13 of <31:13>, is enabled. cfr1<14>: auto clear frequency accumulator bit. when cfr1<14> = 0 ( default ), a new delta frequency word is applied to the input, as in norm a l operation, but not loaded into the accum ulator. rev . p r b 1/30/03 page 18 analog devices , inc.
preliminary technical data AD9953 when cfr1<14> = 1, this bit autom a tically synchronously clears (loads zeros into) the frequency accum u lator for one cycle upon reception of the i/o update sequence indicator. cfr1<13>: autoclear phase accumulator bit. when cfr1<13> = 0 (default) , a new frequency tuning word is applied to the inputs of the phase accumulator, but not loaded into th e accumulator. when cfr1<13> = 1, this bit autom a tically synchronously clears (loads zeros into) the phase accumulator for one cycle upon reception of the i/o update sequence indicator. cfr1<12>: sine/cosine select bit. when cfr1<12> = 0 (default) , the angle-to-am p litude conversion logic em ploys a cosine function. when cfr1<12> = 1, the angle-to-am p litude conversion logic em ploys a sine function. cfr1<11>: clear frequency accum u lator. when cfr1<11> = 0 (default) , the frequency accum ulator functions as norm a l. when cfr1<11> = 1, the frequency accumulator memory elements are asynchronously cleared. cfr1<10>: clear phase accumulator. when cfr1<10> = 0 (default) , the phase accum ulator functions as norm a l. when cfr1<10> = 1, the phase accum u la tor m e m o ry elem ents are asynchronously cleared. cfr1<9>: sdio input only. when cfr1<9> = 0 ( default ), the sdio pin has bi-directional operation (2-wire serial program m i ng m ode). rev . p r b 1/30/03 page 19 analog devices , inc.
preliminary technical data AD9953 when cfr1<9> = 1, the serial data i/o pin (sdio) is configured as an input only pin (3-wire serial program m i ng m ode). cfr1<8>: lsb first. when cfr1<8> = 0 ( default ), msb first format is active. when cfr1<8> = 1, the serial interface a ccepts serial data in lsb first format. cfr1<7>: digital power down bit. when cfr1<7> = 0 ( default ), all digital functions and clocks are active. when cfr1<7> = 1, all non-io digital f unctionality is suspended and all heavily loaded clocks are stopped. this bit is inte nded to lower the digital power to nearly zero, without shutting down the pll cl ock multiplier function or the dac. cfr1<5>: dac power down bit. when cfr1<5> = 0 ( default ), the dac is enabled for operation. when cfr1<5> = 1, the dac is disabled and is in its lowest power dissipation state. cfr1<4>: clock input power down bit. when cfr1<4> = 0 ( default ), the clock input circuitry is enabled for operation. when cfr1<4> = 1, the clock input circuitr y is disabled and the device is in its lowest power dissipation state. cfr1<3>: external power down mode. when cfr1<3> = 0 (default) the external power down mode selected is the ?fast recovery power down? m ode. in this m ode , when the pwrdwnctl input pin is high, the digital logic and the dac digital logic are powered down. the dac bias circuitry, comparator, pll, oscillator, a nd clock input circuitry is not powered down. when cfr1<3> = 1, the external power down m ode selected is the ?full power down? m ode. in this m ode, when the pwrdwn ctl input pin is high, all functions are powered down. this includes the dac and pll, which take a significant am ount of tim e to power up. rev . p r b 1/30/03 page 20 analog devices , inc.
preliminary technical data AD9953 cfr1<1>: syncclk disable bit. when cfr1<1> = 0 (default) , the syncclk pin is active. when cfr1<1> = 1, the syncclk pin assum e s a static logic 0 state (disabled). in this state the pin drive logic is shut dow n to keep noise generated by the digital circuitry at a m i nim u m . however, the synchronization circuitry rem a ins active (internally) to maintain normal device timing. cfr1<0>: not used. leave at 0. note: assertion of this bit m a y cause th e syncclk pin to m o m e ntarily stop generating a sync cloc k signal. the device will not be oper a tional dur ing the r e - s y n chr onization per i od. control functi on regi ster #2 (cfr2) the cfr2 is com p rised of three bytes located in parallel addresses 06h-04h. the cfr2 is used to control the various functions, fe atures, and m odes of the AD9953, prim arily related to the analog sections of the chip. all bits of the cfr2 will be routed direc tly to the analog section of the AD9953 as a single 24-bit bus labeled cfr2<23:0>. cfr2<11>: high speed sync enable bit. when cfr2<11> = 0 (default) the high speed sync enhancement is off. when cfr2<11> = 1, the high speed sync enhancem ent is on. see the synchroniz ing multiple AD9953s section of this document for details. cfr2<10>: hardware manual sync enable bit. when cfr2<10> = 0 (default) the hardware manual sync function is off. when cfr2<11> = 1, the hardware manual s ync function is enabled. while this bit is set, a rising edge on the sync_in pi n will cause the device to advance the sync_clk rising edge by one refclk cycl e. unlike the software manual sync bit, this bit does not self-clear. once the hardware m a nual sync m ode is enabled, it will stay enabled until this bit is cleared. see the synchroniz ing multiple AD9953s section of this document for details. rev . p r b 1/30/03 page 21 analog devices , inc.
preliminary technical data AD9953 cfr2<9>: crystal out enable bit. when cfr2<9> = 0 (default) the crystal out pin is inactive. when cfr2<9> = 1, the crystal out pin is ac tive. when active, the crystal oscillator circuitry output drives the crystal out pin, which can be connected to other devices to produce a reference frequency. cfr2<8>: dac prim e data disable bit. when cfr2<8> = 0 ( default ), the dac prime data is enabled for operation. when cfr2<8> = 1, the dac prime data is not generated and these outputs rem a in logic zeros. cfr2<7:3>: reference clock multiplier control bits. see the phase locked loop (pll) section of this document for details. cfr2<2>: vco gain control bit. this bit is us ed to control the gain setting on the vco. cfr<1:0>: charge pump gain control bits. these bits are used to control the gain setting on the charge pum p. other register descriptions amplitude scale factor (asf) the asf register stores the 2-bit auto ramp rate speed value asf<15:14> and the 14-bit am plitude scale factor asf<13:0> used in the output shaped keying (osk) operation. in auto osk operation, that is cfr1<24> = 1, asf < 15:14> tells the osk block how m a ny am plitude steps to take for each incremen t or decrement. asf<13:0> sets the maximum value achievable by the osk internal multiplier. in manual osk mode , that is cfr1<24>=0, asf<15:14> have no affect. asf <13:0> provide the out put scale factor directly. if the osk enable bit is cleared, cfr1<25>=0, this register has no affect on device operation. amplitude ramp rate (arr) the arr register stores the 8-bit am plitude ram p rate used in the auto osk mode, that is cfr1<25>=1, cfr<24>=1. this register program s the rate the am plitude scale factor counter increments or decrements. in the osk is set to manual mode, cfr1<25>=1 cfr<24>=0, or if osk enable is cleared cfr1< 25>=0, this register has no affect on device operation. rev . p r b 1/30/03 page 22 analog devices , inc.
preliminary technical data AD9953 frequency tuning word 0 (ftw0) the frequency tuning word is a 32-bit register that controls the rate of accumulation in the phase accumulator of the dds core. its specific role is dependent on th e device mode of operation. phase offset word (pow) the phase offset word is a 14-bit register that st ores a phase offset value. this offset value is added to the output of the phase accumulator to o ffset the current phase of the output signal. the exact value of phase offset is given by the following form ula: ? ? ? ? ? ? = 360 * 2 14 pow when the ram enable bit is set, cfr1<31> = 1, and the ram destination is cleared, cfr1<30>=0, the ram supplies the phase offset wo rd and this register has no affect on device operation. frequency tuning word 1 (ftw1) the frequency tuning word is a 32-bit register that controls the rate of accumulation in the phase accumulator of the dds core. its specific role is dependent on th e device mode of operation. ram segment control words 0,1,2,3 (rscw0) (rscw1) (rscw2), (rscw3) registers h?07, h?08, h?09 and h?0a act as th e ram segment control words, rscw0, rscw1, rcsw2 and rcsw3 respectively. each of the ram segm ent control words contains a 3-bit mode control value, a ?no dwell? bit, a 10-bit beginning address, a 10-bit final address and a 16-bit address ramp rate. please see the secti on on ram m odes of operation for details on how each of these values works in th e various ram modes of operation. ram the AD9953 incorporates a 1024x32 block of sram. the ram is bi-directional single- port. that is to say, both read and write opera tions from and to the ram are valid, but they cannot occur sim u ltaneously. write operations from the serial i/o port have precedence, and if an attempt to write to ram is made duri ng a read operation, the read operation will be halted. the ram is controlled in multiple ways, dictated by modes of ope ration described in the ram segment control word <7:5> as well as data in the control function register. read/write control for the ram will be descri bed for each mode supported. when the ram enable bit (cfr1<31>) is set, th e ram output optionally drives the input to the phase accumulator or the phase offset adder, depe nding upon the state of the ?ram destination? bit (cfr1<30>). if cfr1<30> is a logic one, th e ram output is connected to the phase offset adder and supplies the phase offset control word(s ) for the device. when cfr1<30> is logic zero (default condition), the ram output is connected to the input of the phase accum u lator and supplies the frequency tuning word(s) for the devi ce. when the ram output drives the phase accumulator, the phase offset wo rd (pow, hex address 05h) drives the phase-offset adder. rev . p r b 1/30/03 page 23 analog devices , inc.
preliminary technical data AD9953 sim ilarly, when the ram output drives the phase offset adder the frequency tuning word (ftw, hex address 04h) drives the phase accumulator. when cfr1<31> is logic zero, the ram is inactive unless being written to via the serial por t. the power up state of the AD9953 is single tone mode, in which the ram enable bit is in active. the ram is segm ented into four unique slices controlled by the profile<1:0> input pins. all ram writes/reads, unless otherwise specified, are controlled by the profile<1:0> input pins and the respective ram segment control word . the ram can be written to during normal operation but any io operation that commands the ram to be written immediately suspends read operation from the ram, causing the current m ode of operation to be non-functional. this excludes single tone m ode, as the ram is not read in this m ode . modes of operation single tone mode in single tone m ode, the dds core uses a single t uning word. whatever value is stored in ftw0 is supplied to the phase accumulator. this value ca n only be changed static ally, which is done by writing a new value to ftw0 and issuing an i/ o update. phase adjustm e nt is possible through the phase offset register. ram controlled modes of operation direct switch mode direct switch mode enables fsk or psk m odul ation. the AD9953 is program m e d for direct switch mode by writing the ram enable bit tr ue and program m i ng the ram segm ent mode control bits of each desired profile to logic 000(b ). this mode simply reads the ram contents at the ram segm ent beginning address for the current profile. no address ram p ing is enabled in direct switch m ode. to perform 4-tone fsk, the user program s each ram segment control word for direct switch mode and a unique beginning address value. in a ddition, the ram enable bit is written true which enables the ram and the ram destination bit is written false, setting the ram output to be the frequency tuning word. the profile<1:0> inputs are th e 4-tone fsk data inputs. when the profile is changed, the frequency tuning word stored in the new profile is loaded into the phase accumulator and used to increment the currently stored value in a phase continuous fashion. the phase offset word drives the phase-offset adde r. 2-tone fsk is accom p lished by using only one profile pin for data. program m i ng the AD9953 for psk m odulation is sim ila r to fsk except the ram destination bit is set to a logic 1, enabling the ram output to driv e the phase offset adder. the ftw drives the input to the phase accumulator. toggling the prof ile pins changes (modulates) the current phase rev . p r b 1/30/03 page 24 analog devices , inc.
preliminary technical data AD9953 value. the upper 14-bits of the ram drive the phase adder (bits <31:18>). bits <17:0> of the ram output are unused when the ram destination b it is set. the ?no dwell? bit is a don?t care in direct switch mode. ram p -up mode ramp-up mode, in conjunction with the segmente d ram capability, allows up to four different ?sweep profiles? to be program m e d into th e AD9953. the AD9953 is program m e d for ram p -up m ode by writing the ram enable bit true and pr ogram m i ng the ram mode control bits of each profile to be used to logic 001(b). as in all m odes that enable the m e m o ry, the ram destination bit controls whether the ram output drives the phase accum u lator or the phase offset adder. upon starting a sweep (via an i/o update or cha nge in profile bits), the ram address generator loads the ram segm ent beginning address bits of the current rscw, driving the ram output from this address and the ramp rate timer lo ads the ram segment address ramp rate bits. when the ramp rate timer finishes a cycle, th e ram address generator increm ents to the next address, the tim er reloads the ram p rate bits and begins a new countdown cycle. this sequence continues until the ram address generator has in cremented to an address equal to the ram segm ent final address bits of the current rscw. if the ?no dwell? bit is clear, when the ram addr ess generator equals the final address, the generator stops incrementing as the terminal fre quency has been reached. the sweep is complete and does not re-start until an i/o update or change in profile is detected to enable another sweep from the beginning to the final ram address as described above. if the ?no dwell? bit is set, when the ram addre ss generator equals the final address, after the next ramp rate timer cycle the phase accumulator is cleared. the phase accumulator remains cleared until another sweep is initiated via an i/o update input or change in profile. notes to the ramp-up mode: 1) the user m u st insure that the beginning address is lower than the final address. 2) changing profiles automatically terminates the current sweep and starts the next sweep. 3) the AD9953 offers no output si gnal indicating when a term inal frequency has been reached. 4) setting the ram destination bit true such that the ram output drives the phase-offset adder is valid. while the above discussion describe s a frequency sweep, a phase sweep operation is also available. another application for ram p -up m ode is non- sym m e trical fsk m odulation. with the ram configured for two segm ents, using the profile<0 > bit as the data input allows non-sym m e trical ramped fsk. b i - d i r e c t i o n a l r a m p mode rev . p r b 1/30/03 page 25 analog devices , inc.
preliminary technical data AD9953 bi-directional ram p m ode allows the AD9953 to offer a sym m e trical sweep between two frequencies using the profile<0> signal as the c ontrol input. the AD9953 is program m e d for bi- directional ram p m ode by writing the ram enable bit true and the ram mode control bits of rscw0 to logic 010(b). in bi-directional ram p m ode, the profile<1> input is ignored and the profile<0> input is the ram p direction indicator. in this m ode, the m e m o ry is not segm ented and uses only a single beginning and final address. the address registers that affect the control of the ram are located in the rscw a ssociated with profile 0. upon entering this m ode (via an i/o upda te or changing profile<0>), the ram address generator loads the ram segm ent beginning addre ss bits of rscw0 and the ram p rate tim e r loads the ram segment address ramp rate b its. the ram drives data from the beginning address and the ram p rate tim er begins to count down to 1. while operating in this m ode, toggling the profile<0> pin does not cause the device to gene rate an internal i/o update. that is to say, when the profile<0> pin is acting as the ramp dir ection indicator, any transfer of data from the i/o buffers to the internal registers can only be initiated by a rising edge on the i/o update pin. ram address control now is a function of the prof ile<0> input. when the profile<0> bit is a logic one, the ram address generator increm ents to the next address when the ramp rate timer completes a cycle (and reloads to start the timer again). as in the ram p -up m ode, this sequence continues until the ram address generator has increm ented to an address equal to the final address as long as the profile<0> input rem a ins high . if the profile<0> input goes low, the ram address generator immediately decrements and the ramp rate timer is reloaded. the ram address generator will continue to decrem ent at the ramp rate period until the ram address is equal to the beginning address as long as th e profile<0> input rem a ins low . the sequence of ram p ing up and down is controlled via the profile<0> input signal for as long as the part is program m e d into this m ode. the no dwell bit is a ?don?t care? in this m ode as is all data in the ram segment control words associated with profiles 1,2,3. only the information in the ram segm ent control word for profile 0 is used to control the ram in the bi-directional ramp mode. notes to the bi-directional ramp mode: 1) the user m u st insure that the beginning address is lower than the final address. 2) issuing an i/o update automatically term inates the current sweep causing the starting address to be reloaded and the ramp rate timer to initialize. 3) setting the ram destination bit true such th at the ram output drives the phase-offset adder is valid. while the above discussion describe s a frequency sweep, a phase sweep operation is also available. c o n t i n u o u s b i - d i r e c t i o n a l r a m p mode rev . p r b 1/30/03 page 26 analog devices , inc.
preliminary technical data AD9953 continuous bi-directional ram p m ode allows the AD9953 to offer an autom a tic sym m e trical sweep between two frequencies. the AD9953 is pr ogram m e d for continuous bi-directional ram p m ode by writing the ram enable bit true and the ra m mode control bits of each profile to be used to logic 011(b). upon entering this m ode (via an i/o update or changing profile<1:0>), the ram address generator loads the ram segm ent beginning addre ss bits of the current rscw and the ram p rate timer loads the ram segment address ramp rate bits. the ram drives data from the beginning address and the ram p rate tim er begins to count down to 1. when the ram p rate tim er completes a cycle, the ram address generator increm ents to the next addre ss, the timer reloads the ramp rate bits and continues counting down. this sequence continues until the ram address generator has increm ented to an address equal to the ram segment final address bits of the current rscw. upon reaching this terminal addr ess, the ram address generator will decrement in value at the ramp rate un til it reaches the ram segment beginning address. upon reaching the beginning address, the entire sequence repeats. the entire sequence repeats for as long as the part is program m e d for this m ode. the no dwell bit is a ?don?t care? in this m ode. in general, this m ode is identical in control to the bi-directional ram p mode except the ram p up and down is auto matic (no external control via the profile<0> input) and switching profiles is valid. once in this m ode, the address generator ram p s from beginning address to final address back to beginni ng address at the rate program m e d into the ram p rate register. this m ode enables generation of an automatic saw tooth sweep characteristic. notes to the continuous bi-directional ram p m ode: 1) the user m u st insure that the beginning address is lower than the final address. 2) changing profiles or issuing an i/o update automatically terminat es the current sweep and starts the next sweep. 3) setting the ram destination bit true such th at the ram output drives the phase-offset adder is valid. while the above discussion describe s a frequency sweep, a phase sweep operation is also available. continuous re-circulate mode continuous re-circulate m ode allows the AD9953 to offer an autom a tic, continuous unidirectional sweep between two frequencies. the AD9953 is pr ogram m e d for continuous re-circulate m ode by writing the ram enable bit true and the ram mode control bits of each profile to be used to logic 100(b). upon entering this m ode (via an i/o update or changing profile<1:0>), the ram address generator loads the ram segm ent beginning addre ss bits of the current rscw and the ram p rate timer loads the ram segment address ramp rate bits. the ram drives data from the rev . p r b 1/30/03 page 27 analog devices , inc.
preliminary technical data AD9953 beginning address and the ram p rate tim er begins to count down to 1. when the ram p rate tim er completes a cycle, the ram address generator increm ents to the next addre ss, the timer reloads the ramp rate bits and continues counting down. this sequence continues until the ram address generator has increm ented to an address equal to the ram segment final address bits of the current rscw. upon reaching this terminal addr ess, the ram address generator reloads the ram segm ent beginning address bits and the sequence repeats. the sequence of circulating through the specified ram addresses repeats for as long as the part is program m e d for this m ode. the no dwell bit is a don?t care in this m ode. notes to the continuous re-circulate m ode: 1) the user m u st insure that the beginning address is lower than the final address. 2) changing profiles or issuing an i/o update automatically terminates the current sweep and starts the next sweep. 3) setting the ram destination bit true such th at the ram output drives the phase-offset adder is valid. while the above discussion describe s a frequency sweep, a phase sweep operation is also available. r a m c o n t r o l l e d m o d e s o f o p e r a t i o n s u m m a ry the AD9953 offers 5 m odes of ram controlle d operation, as shown in table 3 below. rscw<7:5> (binary) m o d e n o t e s 000 direct switch mode no sweeping, profiles valid, no dwell invalid 001 ram p up sweeping, profiles valid, no dwell valid 010 bi-directional ram p sweeping, profile<0> is a direction control bit, no dwell invalid 0 1 1 c o n t i n u o u s bi- directional ram p sweeping, profiles valid, no dwell invalid 1 0 0 c o n t i n u o u s r e - c i r c u l a t e sweepi ng, profiles valid, no dwell invalid 101,110,111 open invalid m ode ? default to direct switch table 3 ram modes of operation internal profile control the AD9953 offers a mode in which a composite frequency sweep can be built, for which the timing control is software programmable. the ?i nternal profile control? capability disengages the rev . p r b 1/30/03 page 28 analog devices , inc.
preliminary technical data AD9953 profile<1:0> pins and enables the AD9953 to take control of switching between profiles. modes are defined that allow continuous or single burst pr ofile switches for three com b inations of profile selection bits. these are listed in the table belo w. when the any of the cfr1<29:27> bits are active, the internal profile control m ode is engaged. when the internal profile control mode is e ngaged, the ram segm ent mode control bits are ?don?t care? and the device operates all profiles as if these m ode control bits were program m e d for ram p -up m ode. switching between profiles occu rs when the ram address generator has exhausted the m e m o ry contents for the current profile. cfr1<29:27> (binary) mode description 000 internal control inactive 001 internal control active, single burst, activate profile 0, then 1, then stop 010 internal control active, single burst, activate profile 0, then 1, then 2, then stop 011 internal control active, single burst, activate profile 0, then 1, then 2, then 3, then stop 100 internal control active, continuous, activate profile 0, then 1, then loop starting at 0. 101 internal control active, continuous, ac tivate profile 0, then 1, then 2, then loop starting at 0. 110 internal control active, continuous, ac tivate profile 0, then 1, then 2, then 3, then loop starting at 0 1 1 1 i n v a l i d table 4 internal profile control a single burst m ode is one in which the com posite sweep is executed once. for example, assume the device is programmed for ramp-up mode a nd the cfr1<29:27> bits are written to 010(b). upon receiving an i/o update, the internal contro l logic signals the device to begin executing the ram p -up m ode sequence for profile 0. upon reaching the ram segm ent final address value for profile 0, the device automatically switches to profile 1 and begins executing that ram p -up sequence. upon reaching the ram segment fina l address value for profile 1, the device autom a tically switches to profile 2 and begins ex ecuting that ram p -up sequence. when the ram segm ent final address value for profile 2 is r eached, the sequence is over and the com posite sweep has com p leted. issuing another i/ o update re-starts the burst process. rev . p r b 1/30/03 page 29 analog devices , inc. a continuous internal profile control m ode is one in which the com posite sweep is continuously executed for as long as the device is program m e d in to that m ode. using the exam ple above, except programming the cfr1<29:27> bits to 101(b), th e operation would be identical until the ram
preliminary technical data AD9953 segm ent final address value for profile 2 is r eached. at this point, instead of stopping the sequence, it repeats starting with profile 0. programming AD9953 features phase offset control a 14-bit phase-offset ( ) m a y be added to the output of the phase accum u lator by m eans of the control registers. this feature provides the user with three different m e thods of phase control. the first m e thod is a static phase adjustm e nt, where a fixed phase-offset is loaded into the appropriate phase-offset register a nd left unchanged. the result is th at the output signal is offset by a constant angle relative to the nominal signal. th is allows the user to phase align the dds output with some external signal, if necessary. the second m e thod of phase control is where the us er regularly updates the phase-offset register via the i/o port. by properly m odifying the pha se-offset as a function of time, the user can im plem ent a phase m odulated output signal. ho wever, both the speed of the i/o port and the frequency of sysclk lim it the rate at whic h phase m odulation can be perform ed. the third m e thod of phase control involves the ram and the profile input pins. the AD9953 can be configured such that the ram drives the phase ad just circuitry. the user can control the phase offset via the ram in an identical manner allo wed for frequency sweeping. see the ram control and the sweep modes of operation sections for details. phase/amplitude dithering the AD9953 dds core includes optional phase and/ or amplitude dithering controlled via the cfr1<20:16> bits. phase dithering is the random ization of the state of the least significant bits of each phase word. phase dithering reduces spurious signal strengt h caused by phase truncation by spreading the spurious energy over the entire spectrum . the downsid e to dithering is a rise in the noise floor. amplitude dithering is similar, except it a ffects the output signal routed to the dac. the AD9953 uses a 32-bit linear feedback shift re gister (lfsr), shown in figure 7 below, to generate the pseudo random binary sequence that is used for both pha se and amplitude dither data. the lfsr will generate, at the sync_clk rate, the pseudo random sequence only if dithering is enabled. the enable signal is the 4-input or of the dithering control bits (cfr1<20:16>). rev . p r b 1/30/03 page 30 analog devices , inc.
preliminary technical data AD9953 phase dithering is independently controlled on the four least significant bits of the phase word routed to the angle rotation function. that is, any or all of the phase word four least significant bits m a y be dithered or not dithered, controlled by th e user via the serial port. specifically, the cfr1<19> bit controls the phase dithering enab le function of the phase word <16> bit. the cfr1<18> bit controls the phase dithering enab le function of the phase word <15> bit. the cfr1<17> bit controls the phase dithering enab le function of the phase word <14> bit. the cfr1<16> bit controls the phase dithering enable function of the phase word <13> bit. this enable function is such that if the bit is high, dithering is enabled. if the bit is low, dithering is not enabled. am plitude dithering uses one control bit to enable or disable dithering. if the am plitude dither enable bit (cfr1<20>) is logic 0, no am plitude dithering is enabled and the data from the dds core is passed unchanged. when high, amplitude dithering is enabled. shaped on-off keying general description: the shaped on-off keying function of the AD9953 allows the user to control the ram p -up and ram p -down tim e of an ? on-off? em ission from the dac. this function is used in ?burst transm issions? of digital data to reduce the adverse spectral im pact of short, abrupt bursts of data. auto and manual shaped on-off keying m odes ar e supported. the auto m ode generates a linear scale factor at a rate determined by the am plitude ram p rate (arr) register controlled by an external pin (osk). manual mode allows the us er to directly control the output amplitude by writing the scale factor value into the amp litude scale factor (asf) register (asf). the shaped on-off keying function m a y be bypassed (disabled) by clearing the osk enable bit (cfr1<25>=0). the m odes are controlled by two bits located in th e m o st significant byte of the control function register (cfr). cfr1<25> is the shaped on-off ke ying enable bit. when cfr1<25> is set, the output scaling function is enable d; cfr1<25> bypasses the function. cfr1<24> is the internal shaped on-off keying active bit. wh en cfr1<24> is set, internal shaped on-off keying m ode is active; cfr1<24> cleared is ex ternal shaped on-off keying mode active. cfr1<24> is a ?don?t care? if the shaped on-off keyi ng enable bit (cfr1<25>) is cleared. the power up condition is shaped on-off keying disabled (cfr1<25> = 0). figure c below shows the block diagram of the osk circuitry. rev . p r b 1/30/03 page 31 analog devices , inc.
preliminary technical data AD9953 co s(x ) dd s co re to d a c osk en able cfr<25> 0 1 amplit u de scale f a ct or r e gist er (asf ) 0 1 0 0 1 out hold up /dn osk pi n a m plitud e ramp rate registe r (arr ) loa d data en load os k timer cfr1<26> sy nc clo c k clock inc/dec ena b le ra mp rat e time r aut o scale factor ge nerator auto o s k ena b le cfr<24> figure c. on-off shaped keying, block diagram auto shaped on-off keying m ode operation: the auto shaped on-off keying mode is active wh en cfr1<25> and cfr1<24> are set. when auto shaped on-off keying m ode is enabled, a si ngle scale factor is internally generated and applied to the multiplier input for scaling the output of the dds core block (see figure 9 above). the scale factor is the output of a 14-bit counter which increm ents/decrem e nts at a rate determ ined by the contents of the 8-bit output ram p rate regist er. the scale factor increases if the osk pin is high, decreases if the pin is low. the scale factor is an unsigned value such that all zeros multiplies the dds core output by 0 (decimal) and 3fffh multiplies the dds core output by 16383 decimal. for those users who use the full am plitude (14-bits ) but need fast ramp rates, the internally generated scale factor step size is controlled vi a the asf<15:14> bits. the table below describes the increment/decrement step size of the internally generated scale factor per the asf<15:14> bits. rev . p r b 1/30/03 page 32 analog devices , inc.
preliminary technical data AD9953 asf<15:14> (binary) increment/decrement size 0 0 1 0 1 2 1 0 4 1 1 8 table 5 auto-scale factor internal step size a special feature of this mode is that the m a xim u m output am plitude allowed is lim ited by the contents of the am plitude scale factor register. th is allows the user to ra mp to a value less than full scale. o s k r a m p rate tim e r the osk ram p rate tim er is a loadable down count er, which generates the clock signal to the 14-bit counter that generates the internal scale factor. th e ram p rate tim er is load ed with the value of the asfr every tim e the counter reaches 1 (decim a l). this load and count down operation continues for as long as the tim er is enabled unless the tim er is forced to load before reaching a count of 1. if the load osk tim e r bit (cfr1<26>) is set, the ram p rate tim er is loaded upon an i/o update, change in profile input or upon reaching a value of 1. the ram p tim er can be loaded before reaching a count of 1 by three methods. method one is by changing the osk input pin. when the osk input pin changes state the asfr value is loaded into the ram p rate tim er, wh ich then proceeds to count down as norm a l. the second m e thod in which the sweep ram p rate tim er can be loaded before reaching a count of 1 is if the load osk timer bit (cfr1<26>) bit is set and an i/o update (or change in profile) is issued. the last m e thod in which the sweep ram p rate tim er can be loaded before reaching a count of 1 is when going from the inactive auto shaped on-off keying m ode to the active auto shaped on-off keying mode. that is, when the sweep enable bit is being set. external shaped on-off keying m ode operation: the external shaped on-off keying mode is enabled by writing cfr1<25> to a logic 1 and writing cfr1<24> to a logic 0. when configured for external shaped on -off keying, the content of the asfr becomes the scale factor for the da ta path. the scale factors are synchronized to sync_clk via the i/o update functionality. rev . p r b 1/30/03 page 33 analog devices , inc.
preliminary technical data AD9953 sy nchronization; register updates (i/o update) functionality of the syncclk and i/o update data into the AD9953 is synchronous to the sync _clk signal (supplied externally to the user on the sync_clk pin). the i/o_update pin is sam p led on the rising edge of the sync_clk. internally, sysclk is fed to a divide-by-4 fre quency divider to produce the sync_clk signal. the sync_clk signal is provided to the user on th e sync_clk pin. this enables synchronization of external hardware with the device?s intern al clocks. this is accomplished by forcing any external hardware to obtain its tim ing from s ync_clk. the i/o update signal coupled with sync_clk is used to transfer internal buffer conten ts into the control registers of the device. the com b ination of the sync_clk and i/o update pins provides the user with constant latency relative to sysclk and also ensures phase continuity of the analog output signal when a new tuning word or phase offset value is asserted. figure e de m onstrates an i/o update tim ing cycle and synchronization. notes to synchronization logic: 1) the i/o update signal is edge detected to generate a single rising edge clock signal that drives the register bank flops. the i/o update signal has no constraints on duty cycle. the minimum low time on i/o up date is one sync_clk clock cycle. 2) the i/o update pin is setup and held ar ound the rising edge of sync_clk and has zero hold tim e and 10ns setup tim e. rev . p r b 1/30/03 page 34 analog devices , inc.
preliminary technical data AD9953 0 1 0 sy nc clk disa ble d q d q d q os k p r ofile<1:0> i/o upda t e e dge detectio n lo gic synccl k gating register me m o ry i/o buff er latches sc lk sdi cs to core logic sy sclk 4 figure d- i/o synchroniz ation block diagram data [1] data[ 1 ] d a t a(2) data (2) d ata(3) dat a ( 3 ) ab sy sc l k sy nclk i/o update data in registe r s data in i/o b u ffers t he device regist ers an i / o u pdate at point a. t h e data is t r an f e rred f r o m the asynch ronously load ed i / o buf fers at p o int b. figure e - i/o synchroniz ation timing diagram rev . p r b 1/30/03 page 35 analog devices , inc.
preliminary technical data AD9953 sy nchronizing multiple AD9953s the AD9953 product allows easy sync hronization of multiple AD9953s. there are three modes of synchronization available to the user: an autom a tic synchronization m ode; a software controlled m a nual synchronization m ode; and a hardware controlled m a nual synchronization m ode. in all cases, when a user wants to synchronize two or m o re devices, the following considerations m u st be observed. first, all units must share a common cl ock source. trace lengths and path im pedance of the clock tree m u st be designed to keep the phase delay of the different clock branches as closely m a tched as possible. second, the i/o update signa l?s rising edge m u st be provided synchronously to all devices in the system . finally, regardless of the internal synchronization m e thod used, the dvdd_i/o supply should be set to 3.3v for all devices that are to be synchronized. avdd and dvdd should be left at 1.8v. in autom a tic synchronization m ode, one device is chosen as a master, the other device(s) will be slaved to this master. when configured in this mode, all the slaves will automatically synchronize their internal clocks to the sync_clk output signal of the m a ster device. to enter autom a tic synchronization m ode, set the slav e device?s autom a tic synchronization bit (cfr1<23>=1). connect the sync_in input(s) to the m a ster sync_clk output. the slave device will continuously update the pha se relationship of its sync_clk until it is in phase with the sync_in input, which is the sync_clk of the m a ster device. when attem p ting to synchronize devices running at sysclk speeds beyond 250msps, th e high-speed sync enhancem ent enable bit should be set (cfr2<11>=1). in software m a nual synchronization m ode, the user forces the device to advance the sync_clk rising edge one sysclk cycle (1/4 sync_clk period). to activate the m a nual synchronization m ode, set the slave device?s soft ware m a nual synchronization bit (cfr1<22> =1). the bit (cfr1<22>) will be immediately cleared. to advance the rising edge of the sync_clk multiple times, this bit will n eed to be set multiple times. in hardware m a nual synchronization m ode, the s ync_in input pin is configured such that it will now advance the rising edge of the sync_clk signal each time the device detects a rising edge on the sync_in pin. to put the device into hardware m a nual synchronization m ode, set the hardware m a nual synchronization bit (cfr2<10>=1 ). unlike the software m a nual synchronization bit, this bit does not self-clear. once the hard ware m a nual synchronization m ode is enabled, all rising edges detected on the sync_in input will caus e the device to advance the rising edge of the sync_clk by one sysclk cycle until this enable bit is cleared (cfr2<10=0). using a single cry s tal to dri ve multiple AD9953 clock inputs the AD9953 crystal oscillator output signal is availa ble on the crystalout pin, enabling one crystal to drive multiple AD9953s. in order to drive mu ltiple AD9953s with one crystal, the crystalout pin of the AD9953 using the external crystal shoul d be connected to the refclk input of the other AD9953. rev . p r b 1/30/03 page 36 analog devices , inc.
preliminary technical data AD9953 the crystalout pin is static until the cfr2<1> bit is set, enabling the output. the drive strength of the crystalout pin is typically very low, so this signal should be buffered prior to using it to drive any loads. serial port operation with the AD9953, the instruction by te specifies read/write operation and register address. serial operations on the AD9953 occur only at the register level, not the byte level. for the AD9953, the serial port controller recognizes the instruction by te register address and autom a tically generates the proper register byte address. in addition, the cont roller expects that all bytes of that register will be accessed. it is a requirement that all bytes of a register be accessed during serial i/o operations, with one exception. the syncio function can be used to abort an io operation thereby allowing less than all bytes to be accessed. there are two phases to a com m unication cycle with the AD9953. phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9953, coincident with the first eight sclk rising edges. the instruction byte provides the AD9953 serial port controller with inform ation regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcom ing data tr ansfer is read or write and the serial address of the register being accessed. [note ? the serial address of the register being accessed is not the same address as the bytes to be written. see th e example operation section below for details]. the first eight sclk rising edges of each com m uni cation cycle are used to write the instruction byte into the AD9953. the rem a ining sclk edges are for phase 2 of the com m unication cycle. phase 2 is the actual data transfer between th e AD9953 and the system controller. the num ber of bytes transferred during phase 2 of the com m unica tion cycle is a function of the register being accessed. for example, when accessing the control f unction register 2, which is three bytes wide, phase 2 requires that three bytes be transferred. if accessing the frequency tuning word, which is four bytes wide, phase 2 requires th at four bytes be transferred. af ter transferring all data bytes per the instruction, the communi cation cycle is completed. at the com p letion of any com m unication cycle, th e AD9953 serial port controller expects the next 8 rising sclk edges to be the instruction byte of the next com m unication cycle.all data input to the AD9953 is registered on the rising edge of sc lk. all data is driven out of the AD9953 on the falling edge of sclk. figures 34 - 37 are useful in understanding the general operation of the AD9953 serial port. rev . p r b 1/30/03 page 37 analog devices , inc.
preliminary technical data AD9953 instruction by te the instruction byte contains the following in form ation as shown in the table below: instruction byte information m s b d 6 d 5 d 4 d 3 d 2 d 1 l s b r / w b x x a 4 a 3 a 2 a 1 a 0 table 6 instruction byte rev . p r b 1/30/03 page 38 analog devices , inc.
preliminary technical data AD9953 r/-wb?bit 7 of the instruction byte determines wh ether a read or write data transfer will occur after the instruction byte write. logic high indicat es read operation. logic zero indicates a write operation. x, x?bits 6 and 5 of the instruction byte are don?t care. a4, a3, a2, a1, a0?bits 4, 3, 2, 1, 0 of the in struction byte determ ine which register is accessed during the data transfer portion of the com m unications cycle. seri al int e rf ace port pi n descri pt i on sclk ? serial clock. the serial clock pin is us ed to synchronize data to and from the AD9953 and to run the internal state m a chines. sclk m a xim u m frequency is 25 mhz. csb ? chip select bar. active low input that allo ws m o re than one device on the sam e serial communications line. the sdo and sdio pins will go to a high impedance state when this input is high. if driven high during any communications cycle, that cy cle is suspended until cs is reactivated low. chip select can be tied low in systems that maintain control of sclk. sdio ? serial data i/o. data is always written into the AD9953 on this pin. however, this pin can be used as a bi-directional data line. bit 7 of register address 0h contro ls the configuration of this pin. the default is logic zero, which c onfigures the sdio pin as bi-directional. sdo ? serial data out. data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case wher e the AD9953 operates in a single bi-directional i/o m ode, this pin does not output data and is set to a high im pedance state. syncio ? synchronizes the i/o port state m a chines w ithout affecting the addressable registers contents. an active high input on the sync i/o pin causes the current com m unication cycle to abort. after sync i/o returns low (logic 0) another com m unication cycle m a y begin, starting with the instruction byte write. msb/lsb transqfers the AD9953 serial port can support both m o st signifi cant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by the control register 00h<8> bit. the default value of control register 00h<8> is low (m sb first). when control register 00h<8> is set high, the AD9953 serial port is in lsb first form at. the instruction byte must be written in the form at indicated by control register 00h<8>. that is, if the AD9953 is in lsb first m ode, the instruction byte must be written from least si gnificant bit to most significant bit. for msb first operation, the serial port controller will generate the most significant byte (of the specified register) address first followed by the ne xt lesser significant byte addresses until the io rev . p r b 1/30/03 page 39 analog devices , inc.
preliminary technical data AD9953 operation is complete. all data written to (read from) the AD9953 must be (will be) in msb first order. if the lsb mode is active, the serial port controller will generate the least significant byte address first followed by the next greater signi ficant byte addresses until the io operation is complete. all data written to (read from) the AD9953 must be (will be) in lsb first order. exampl e operat i on to write the am plitude scale factor register in msb first form at apply an instruction byte of 02h (serial address is 00010(b)). from this instruction, the internal controller w ill generate an internal byte address of 07h (see the register map) for the fi rst data byte written and an internal address of 08h for the next byte written. since the amplitude sc ale factor register is two bytes wide, this ends the communication cycle. to write the am plitude scale factor register in lsb first form at apply an instruction byte of 40h. from this instruction, the intern al controller will generate an internal byte address of 07h (see the register map) for the first data byte written and an internal address of 08h for the next byte written. since the amplitude scale factor register is tw o bytes wide, this ends the com m unication cycle. ram i/o via serial port accessing the ram via the serial port is identical to any other serial io operation except that the num ber of bytes transferred is determ ined by th e address space between the beginning address and the final address as specified in the current ram segment control word (rscw). the final address describes the m o st significant word addr ess for all io transfers and the beginning address specifies the least significant address. ram i/o supports msb/lsb first operation. when in msb first mode, the first data byte will be for the most significant byte of the memory a ddress described by the final address with the rem a ining three bytes m a king up the lesser significant bytes of that address. the rem a ining bytes come in most significant to least significant, de stined for ram addresses generated in descending order until the final four bytes are written into th e address specified as the beginning address. when in lsb first mode, the first data byte will be for the least significant byte of the memory (specified by the beginning address) with th e rem a ining three bytes m a king up the greater significant bytes of that address. the rem a ining bytes come in least significant to most significant, destined for ram addresses generated in ascending order until the final four bytes are written into the m e m o ry address described by the final address. of course, the bit order for all bytes is least significant to most significant firs t when in the lsb first bit is set. when the lsb first bit is cleared (default) the bit order for all bytes is most significant to least significant. the ram uses serial address 01011(b), so the inst ruction byte to write the ram is 0bh, in msb first notation. as m e ntioned above, the ram a ddresses generated are specified by the beginning and final address of the rscw curren tly selected by the profile<1:0> pins. rev . p r b 1/30/03 page 40 analog devices , inc.
preliminary technical data AD9953 n o t e s on seri al port operat i on 1) the AD9953 serial port configuration bits resi de in bits 8 and 9 of cfr1 (address 00h). the configuration changes immediat ely upon writing to this register. for multi-byte transfers, writing to this register m a y occur during the m i ddle of a com m unication cycle. care m u st be taken to compensate for this new confi guration for the rem a inder of the current communication cycle. 2) the system m u st m a intain synchronization with the AD9953 or the internal control logic will not be able to recognize further instruc tions. for example, if the system sends an instruction byte that describes writing a 2-byte register, then pulses the sclk pin for a 3- byte write (24 additional sclk rising edges), co m m unication synchronization is lost. in this case, the first 16 sclk rising edges after the instruction cycle will properly write the first two data bytes into the AD9953, but the next ei ght rising sclk edges are interpreted as the next instruction byte, not the final byte of the previous com m unication cycle. in the case where synchronization is lost between the system and the AD9953, the sync i/o pin provides a means to re-establish synchronizati on without re-initializing the entire chip. the sync i/o pin enables the user to reset the AD9953 state machine to accept the next eight sclk rising edges to be coincident with the instruction phase of a new com m unication cycle. by applying and rem oving a ?high? signal to the sync i/o pin, the AD9953 is set to once again begin perform ing the com m unication cycle in synchronization with the system . any information that had been written to the AD9953 registers during a valid communication cycle prior to loss of synchronization will remain intact. 3) reading profile registers requires that the profile select pins (profile<1:0>) be configured to select the desired register bank. when reading a register that resides in one of the profiles, the register address acts as an offset to select one of the registers am ong the group of registers defined by the profile. while the profile select pins select the appropriate register group. pow e r dow n functions of the AD9953 the AD9953 supports an externally controlled, or hardware, power down feature as well as the m o re com m on software program m a ble power down bits found in previous adi dds products. the software control power down allows the dac , com p arator, pll, input clock circuitry and the digital logic to be individually power down via unique control bits (cfr1<7:4>). with the exception of cfr1<6>, these bits are not active when the externally controlled power down pin (pwrdwnctl) is high. external power down control is supported on the AD9953 via the pwrdwnctl input pin. when the pwrdwnctl i nput pin is high, the AD9953 will enter a power down m ode based on the cfr1<3> bit. when the pw rdwnctl input pin is low, the external power down control is inactive. rev . p r b 1/30/03 page 41 analog devices , inc.
preliminary technical data AD9953 rev. prb 1/30/03 page 42 analog devices, inc. when the cfr1<3> bit is zero, and the pwrdwnctl input pin is high, the AD9953 is put into a ?fast recovery power down? mode. in this mode , the digital logic and the dac digital logic are powered down. the dac bias circuitry, comparato r, pll, oscillator, and clock input circuitry is not powered down. the comparator can be powered down by setting the comparator power down bit, cfr1<6> =1. when the cfr1<3> bit is high, and the pwrdwnc tl input pin is high, the AD9953 is put into the ?full power down? mode. in this mode, all func tions are powered down. this includes the dac and pll, which take a significant amount of time to power up. when the pwrdwnctl input pin is high, the i ndividual power down bits (cfr1<7>, <5:4>) are invalid (don?t care) and are unused; however the comparator power down bit, cfr1<6>, will continue to control the power-down of the compar ator. when the pwrdwnctl input pin is low, the individual power down bits control th e power down modes of operation. note ? the power down signals are all designed such that a logic 1 indicates the low power mode and a logic zero indicates the active, or powered up mode. the table below indicates the logic level for e ach power down bit that drives out of the AD9953 core logic to the analog section and the digital cloc k generation section of the chip for the external power down operation. control mode active description pwrdwnctl = 0 cfr1<3> don?t care software control digital power down = cfr1<7> comparator power down = cfr1<6> dac power down = cfr1<5> input clock power down = cfr1<4> pwrdwnctl = 1 cfr1<3> = 0 external control, fast recovery power down mode digital power down = 1?b1; comparator power down = 1?b0 or cfr1<6>; dac power down = 1?b0; input clock power down = 1?b0; pwrdwnctl = 1 cfr1<3> = 1 external control, full power down mode digital power down = 1?b1; comparator power down = 1?b1; dac power down = 1?b1; input clock power down = 1?b1; table 7 power down control functions

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